Solid state imaging device

ABSTRACT

The solid state imaging device of this invention includes a pixel unit for outputting, as an analog signal, a voltage signal corresponding to light and an AD converter for converting the analog signal output by the pixel unit into a digital signal. Transistors used in the pixel unit and the AD converter are all N-type MOS transistors. The AD converter includes a booster circuit.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to an NMOS solid state imagingdevice using N-type MOS transistors alone as transistors includedtherein, and more particularly, it relates to a technique to include anAD converter in an NMOS solid state imaging device for realizing adigital signal output function.

[0002]FIG. 16 is a block diagram for showing the internal configurationof a conventional CMOS solid state imaging device. As shown in FIG. 16,the CMOS solid state imaging device 10 includes a pixel unit 11 composedof a plurality of pixels 11 a arranged in a matrix, a vertical scanningunit 12 for outputting a row selection signal for selecting an arbitrarypixel row in the pixel unit 11, and a horizontal scanning unit 13 forreading an analog signal output from each pixel belonging to the pixelrow selected in accordance with the row selection signal. The verticalscanning unit 12 is connected to each pixel row of the pixel unit 11through a first selection signal line 11 b, and the horizontal scanningunit 13 is connected to each pixel column of the pixel unit 11 through asecond selection signal line 11 c. Also, a noise filtering unit 14 forremoving noise from the analog signal output from each pixel of thepixel unit 11 is provided between the pixel unit 11 and the horizontalscanning unit 13. Moreover, the CMOS solid state imaging device 10further includes an amplifier unit 15 for amplifying the analog signalread by the horizontal scanning unit 13, and an AD converter 16 forconverting the analog signal having been amplified by the amplifier unit15 into a digital pixel signal and outputting it to the outside (i.e.,to a signal processor 20). The signal processor 20 transmits pulses andthe like necessary for the operations of respective constitutionelements of the CMOS solid state imaging device 10.

[0003] As compared with the case where an analog pixel signal is output,advantages of outputting a digital pixel signal are, for example, thatan interface portion between the solid state imaging device and thesignal processor typified by a DSP (Digital Signal Processor) is lessinfluenced by noise and that the signal is less degraded. Therefore,many CMOS solid state imaging devices include AD converters (see, forexample, Japanese Laid-Open Patent Publication No. 2000-286706 (pp. 2-5and FIG. 1)).

[0004] Apart from conventional CCD solid state imaging devices and CMOSsolid state imaging devices, development of NMOS solid state imagingdevices has recently been started. In an NMOS solid state imagingdevice, N-type MOS transistors alone are used as transistors included inits circuits. Specifically, an NMOS solid state imaging device isexpected to be a promising solid state imaging device that can befabricated through a largely reduced number of processes necessary forforming wells and transistors in a substrate while keeping its imagingperformances.

[0005]FIG. 17 is a block diagram for showing the internal configurationof a conventional NMOS solid state imaging device. As shown in FIG. 17,the NMOS solid state imaging device 30 includes a pixel unit 31 composedof a plurality of pixels 31 a arranged in a matrix, a vertical scanningunit 32 for outputting a row selection signal for selecting an arbitrarypixel row in the pixel unit 31, and a horizontal scanning unit 33 forreading an analog signal output from each pixel belonging to the pixelrow selected in accordance with the row selection signal. The verticalscanning unit 32 is connected to each pixel row of the pixel unit 31through a first selection signal line 31 b, and the horizontal scanningunit 33 is connected to each pixel column of the pixel unit 31 through asecond selection signal line 31 c. A noise filtering unit 34 forremoving noise from the analog signal output from each pixel of thepixel unit 31 is provided between the pixel unit 31 and the horizontalscanning unit 33. Moreover, the NMOS solid state imaging device 30further includes an amplifier unit 35 for amplifying the analog signalread by the horizontal scanning unit 33 and outputting the amplifiedanalog signal to the outside (i.e., to a signal processor 40). Thesignal processor 40 transmits pulses and the like necessary for theoperations of respective constitution elements of the NMOS solid stateimaging device 30.

[0006] However, it is very difficult, from the viewpoint of keeping aconversion rate, to provide the NMOS solid state imaging device usingN-type MOS transistors alone as transistors with equivalent functions tothose of a CMOS solid state imaging device, and particularly to includean AD converter in the NMOS solid state imaging device. Specifically, asshown in FIG. 17, the conventional NMOS solid sate imaging device doesnot include an AD converter. Therefore, although an NMOS solid stateimaging device is a promising solid state imaging device as describedabove, it can disadvantageously exhibit functions poorer than those of aCMOS solid state imaging device.

SUMMARY OF THE INVENTION

[0007] In consideration of the aforementioned disadvantage, an object ofthe invention is including, in an NMOS solid state imaging device, arapid AD converter having a circuit configuration including N-type MOStransistors alone.

[0008] In order to achieve the object, the solid state imaging device ofthis invention using N-type MOS transistors alone as transistorsincluded therein, includes a pixel unit composed of a plurality ofpixels arranged in a two-dimensional matrix, each of the pixelsincluding a photoelectric converting element for generating charge inresponse to light and an amplifying element for outputting, as an analogsignal, a voltage signal corresponding to the charge generated by thephotoelectric converting element; a selection signal line providedcorrespondingly to each pixel row of the pixel unit; acomparison/storage unit provided correspondingly to each pixel column ofthe pixel unit for converting, into a digital signal, the analog signaloutput from the amplifying element included in each pixel belonging to apixel row selected in the pixel unit and for storing the digital signal;a scanner for selecting and reading the digital signal stored in thecomparison/storage unit in time series; and an amplifier for amplifyingthe read digital signal and outputting the amplified digital signal tothe outside.

[0009] In the NMOS solid state imaging device of this invention, ananalog signal output from the amplifying element of each pixel belongingto a pixel row selected in the pixel unit is rapidly converted into adigital signal in the comparison/storage unit. Therefore, the NMOS solidstate imaging device can attain an AD conversion function equivalent tothat of a CMOS solid state imaging device, and thus, the additionalvalue of the NMOS solid state imaging device can be remarkably improved.

[0010] Preferably, in the solid state imaging device, thecomparison/storage unit includes a comparator, which includes threeinverter circuits using N-type MOS transistors alone and seriallyconnected to one another, and a booster circuit for preventing voltageattenuation of an output signal and accelerating the output signal; inorder to increase a fall speed of an inverter circuit disposed at thefirst stage out of the three inverter circuits, ON resistance of atransistor connected to GND potential is set to be smaller than ONresistance of a transistor connected to power potential in the invertercircuit disposed at the first stage; in order to increase a rise speedof an inverter circuit disposed at the second stage out of the threeinverter circuits, ON resistance of a transistor connected to the powerpotential is set to be smaller than ON resistance of a transistorconnected to the GND potential in the inverter circuit disposed at thesecond stage; and in order to increase a fall speed of an invertercircuit disposed at the third stage out of the three inverter circuits,ON resistance of a transistor connected to the GND potential is set tobe smaller than ON resistance of a transistor connected to the powerpotential in the inverter circuit disposed at the third stage.

[0011] Thus, the comparator is provided with the booster circuit, andthe fall speed from “High” level to “Low” level of the ultimate outputcharacteristic of the inverter circuit disposed at the third stage ofthe comparator is increased. Therefore, even though N-type MOStransistors alone are used, problems of signal voltage levelattenuation, consumption power increase and response speed lowering canbe prevented.

[0012] Preferably, in the solid state imaging device, thecomparison/storage unit includes a memory, which includes a first switchfor reading a counter value on the basis of a signal supplied from thecomparator, a capacitor for storing the read counter value, a secondswitch for transferring the counter value stored in the capacitor, athird switch for deleting the transferred counter value, a fourth switchfor reading the transferred counter value on the basis of a signalsupplied from the scanner, and the amplifier for outputting the readcounter value to the outside, and the amplifier includes a boostercircuit for preventing voltage attenuation of an output signal thereofand accelerating the output signal.

[0013] Thus, circuit elements can be shared in accordance with theoperation characteristics thereof in the memory, resulting in reducingthe circuit scale. Furthermore, since the amplifier is provided with thebooster circuit, even though N-type MOS transistors alone are used, theproblems of the signal voltage attenuation, the consumption powerincrease and the response speed lowering can be prevented, so that theNMOS solid state imaging device can attain performances at the practicallevels.

[0014] Preferably, the solid state imaging device of this inventionfurther includes a pulse generator for generating a pulse signal on thebasis of a column selection signal output from a horizontal scannerincluded in the scanner; and a counter generator for generating thecounter value on the basis of the pulse signal generated by the pulsegenerator.

[0015] Thus, a pulse generation circuit included in an external signalprocessor such as a DSP in a conventional solid state imaging device canbe omitted. Also in this case, when the counter generator is providedwith a booster circuit for preventing voltage attenuation of its outputsignal and accelerating the output signal, the problems of the signalvoltage level attenuation, the consumption power increase and theresponse speed lowering can be more definitely prevented.

[0016] The solid state imaging device of this invention may furtherinclude a ramp waveform generator for generating a ramp signal on thebasis of the pulse signal generated by the pulse generator and thecounter value generated by the counter generator.

[0017] The alternative solid state imaging device of this inventionincludes a pixel unit formed on a semiconductor substrate andoutputting, as an analog signal, a voltage signal corresponding tolight; and an AD converter formed on the semiconductor substrate andconverting the analog signal output from the pixel unit into a digitalsignal, and transistors included in the pixel unit and the AD converterare all N-type MOS transistors, and the AD converter includes a boostercircuit.

[0018] In the alternative NMOS solid state imaging device, an analogsignal output from the pixel unit is converted into a digital signal inthe AD converter. Also, since the AD converter includes the boostercircuit, voltage attenuation of its output pulse can be prevented andthe output pulse can be accelerated. Therefore, the NMOS solid stateimaging device can realize a rapid AD conversion function equivalent tothat of a CMOS solid state imaging device, so that the additional valueof the NMOS solid state imaging device can be remarkably improved.

[0019] Preferably, in the alternative solid state imaging device of thisinvention, the booster circuit includes a transistor whose source ordrain is connected to power potential, and a voltage not less than thepower potential is applied to a gate of the transistor.

[0020] Thus, the transistor of the booster circuit can be placed in acomplete conductive state, and therefore, a signal at “High” level canbe output while preventing the voltage attenuation.

[0021] Preferably, in the alternative solid state imaging device, the ADconverter includes, in addition to the booster circuit, any or all of acomparator, a memory, a pulse generator and a counter generator.

[0022] Thus, a rapid AD converter can be definitely obtained.

[0023] In the case where the AD converter includes a comparator, thecomparator may include an inverter circuit having the booster circuit,the booster circuit may include a first transistor whose source or drainis connected to power potential, and a voltage not less than the powerpotential may be applied to a gate of the first transistor.

[0024] Alternatively, in the case where the AD converter includes acomparator, the comparator may include an inverter circuit having thebooster circuit, the inverter circuit may have a second transistorformed above a well region independent of other well regions, and a gateand a source of the second transistor may be electrically connected tothe well region.

[0025] In the case where the AD converter includes a memory, the memorymay include a plurality of switches, a capacitor and an outputamplifier, the output amplifier may include a booster circuit, thebooster circuit may have a transistor whose source or drain is connectedto power potential, and a voltage not less than the power potential maybe applied to a gate of the transistor. In this case, the memory mayinclude a first switch for reading a counter value on the basis of asignal supplied from the comparator, a capacitor for storing the readcounter value, a second switch for transferring the counter value storedin the capacitor, a third switch for deleting the transferred countervalue, a fourth switch for reading the transferred counter value on thebasis of a signal supplied from the scanner, and an output amplifier foroutputting the read counter value to the outside.

[0026] In the case where the AD converter includes a pulse generator,the pulse generator generates a pulse signal on the basis of a columnselection signal output from a horizontal scanner and may include aplurality of inverter circuits serially connected to one another, aninverter circuit disposed at the ultimate stage out of the plurality ofinverter circuits may include a booster circuit, the booster circuit mayhave a transistor whose source or drain is connected to power potential,and a voltage not less than the power potential may be applied to a gateof the transistor.

[0027] In the case where the AD converter includes a counter generator,the counter generator generates a counter value on the basis of a pulsesignal generated by the pulse generator and may include a plurality ofinverter circuits each having a booster circuit, the. booster circuitmay have a transistor whose source or drain is connected to powerpotential, and a voltage not less than the power potential may beapplied to a gate of the transistor.

[0028] In this manner, according to the present invention, the NMOSsolid state imaging device is provided with the rapid comparison/storageunit, that is, a rapid AD converter, that converts an analog signaloutput from the pixel unit into a digital signal and uses N-type MOStransistors alone. Therefore, even the NMOS solid state imaging devicecan include an AD converter equivalent to that used in a CMOS solidstate imaging device, so that the additional value of the NMOS solidstate imaging device can be remarkably improved.

[0029] In other words, the present invention relates to the technique toinclude an AD converter in a solid state imaging device, and isparticularly useful in application to an NMOS solid state imaging devicefor realizing a digital signal output function.

BRIEF DESCRIPTION OF THE DRAWINGS

[0030]FIG. 1 is a block diagram for showing the schematic configurationof an NMOS solid state imaging device according to an embodiment of theinvention;

[0031]FIG. 2 is a block diagram for showing the schematic circuitconfiguration of a comparator used in the NMOS solid state imagingdevice according to the embodiment;

[0032]FIG. 3 is a block diagram for showing the detailed circuitconfiguration of the comparator used in the NMOS solid state imagingdevice according to the embodiment;

[0033]FIG. 4 is an operation timing chart of the comparator used in theNMOS solid state imaging device according to the embodiment;

[0034]FIG. 5 is a block diagram for showing the schematic circuitconfiguration of a memory used in the NMOS solid state imaging deviceaccording to the embodiment;

[0035]FIG. 6 is a block diagram for showing the detailed circuitconfiguration of the memory used in the NMOS solid state imaging deviceaccording to the embodiment;

[0036]FIG. 7 is an operation timing chart of the memory used in the NMOSsolid state imaging device according to the embodiment;

[0037]FIG. 8 is a block diagram for showing the circuit configuration ofa pulse generator used in the NMOS solid state imaging device accordingto the embodiment;

[0038]FIG. 9 is an operation timing chart of the pulse generator used inthe NMOS solid state imaging device according to the embodiment;

[0039]FIG. 10 is a block diagram for showing the circuit configurationof a counter generator used in the NMOS solid state imaging deviceaccording to the embodiment;

[0040]FIG. 11 is a block diagram for showing the detailed configurationof a frequency divider used in the counter generator in the NMOS solidstate imaging device according to the embodiment;

[0041]FIG. 12 is an operation timing chart of the counter generator usedin the NMOS solid state imaging device according to the embodiment;

[0042]FIG. 13 is a block diagram for showing the circuit configurationof a DA converter used in the NMOS solid state imaging device accordingto the embodiment;

[0043]FIG. 14 is a block diagram for showing the circuit configurationof a ramp waveform generator used in the NMOS solid state imaging deviceaccording to the embodiment;

[0044]FIG. 15 is an operation timing chart of the ramp waveformgenerator used in the NMOS solid state imaging device according to theembodiment;

[0045]FIG. 16 is a block diagram for showing the schematic configurationof a conventional CMOS solid state imaging device;

[0046]FIG. 17 is a block diagram for showing the schematic configurationof a conventional NMOS solid state imaging device; and

[0047]FIG. 18 is a cross-sectional view of a transistor used forconstructing an inverter circuit included in the comparator used in theNMOS solid state imaging device according to the embodiment.

DETAILED DESCRIPTION OF THE INVENTION

[0048] A solid state imaging device according to an embodiment of theinvention, and specifically, an NMOS solid state imaging device thatuses N-type MOS transistors alone as transistors included in itscircuits and includes an AD converter, will now be described withreference to the accompanying drawings.

[0049]FIG. 1 is a block diagram for showing the schematic configurationof the NMOS solid state imaging device of this embodiment.

[0050] As shown in FIG. 1, the NMOS solid state imaging device 100includes a pixel unit 101 composed of a plurality of pixels 101 aarranged in a two-dimensional matrix, a vertical scanner 102 foroutputting a row selection signal for selecting an arbitrary pixel rowin the pixel unit 101, and a horizontal scanner 103 for outputting acolumn selection signal for selecting an arbitrary pixel column in thepixel unit 101. The vertical scanner 102 is connected to each pixel rowof the pixel unit 101 through a first selection signal line 101 b, andthe horizontal scanner 103 is connected to each pixel column of thepixel unit 101 through a second selection signal line 110 c. Althoughnot shown in the drawing, each pixel 110 a of the pixel unit 101includes a photoelectric converter (such as a photo diode) forgenerating charge in response to light and an amplifier (such as anamplifier transistor) for outputting, as an analog signal, a voltagesignal corresponding to the charge generated by the photoelectricconverter.

[0051] As a characteristic of this embodiment, a comparison/storage unit(i.e., a comparator 104 and a memory 105) is provided between the pixelunit 101 and the horizontal scanner 103 correspondingly to each pixelcolumn of the pixel unit 101. The comparison/storage unit converts ananalog signal output from the amplifier of each pixel 101 a belonging tothe pixel row selected in the pixel unit 101 into a digital signal andstores the digital signal. Specifically, the comparator 104 reads ananalog signal from each pixel 101 a belonging to the pixel row selectedin accordance with the row selection signal, and synthesizes the readanalog signal with a ramp signal so that the synthesized signal can becompared with a reference voltage. Also, the memory 105 accepts, as aninput, the comparison result obtained by the comparator 104, and storesa counter value on the basis of the comparison result and reads, as adigital signal, the stored counter value in time series on the basis ofthe column selection signal. As described later, the memory 105 includesan amplifier for amplifying the digital signal and outputting theamplified digital signal to the outside (i.e., to a signal processor150).

[0052] As another characteristic of this embodiment, the NMOS solidstate imaging device 100 further includes a pulse generator 106 forgenerating a pulse signal on the basis of the column selection signalsupplied by the horizontal scanner 103; a counter generator 107 forgenerating the counter value necessary for the memory 105 on the basisof the pulse signal supplied by the pulse generator 106; a DA converter108 for generating an analog signal on the basis of the counter valuesupplied by the counter generator 107; and a ramp waveform generator 109for generating the ramp signal necessary for the comparator 104 on thebasis of the analog signal supplied by the DA converter 108 and thepulse signal supplied by the pulse generator 106. The pulse generator106 transmits the pulse signal also to the pixel unit 101, the verticalscanner 102, the comparator 104 and the memory 105. Also, the signalprocessor 150 provided outside the NMOS solid state imaging device 100transmits given signals to the horizontal scanner 103 and the countergenerator 107.

[0053] In this manner, the comparator 104, the memory 105, the pulsegenerator 106 and the counter generator 107 together form an ADconverter in this embodiment, but the configuration of the AD converteris not limited to this. For example, there is no need for the ADconverter to include all of the comparator 104, the memory 105, thepulse generator 106 and the counter generator 107. Also, as describedlater, the AD converter preferably includes a booster circuit.

[0054] Now, the respective constitution elements of the NMOS solid stateimaging device 100, that is, specifically, the comparator 104, thememory 105, the pulse generator 106, the counter generator 107, the DAconverter 108 and the ramp waveform generator 109, will be described indetail. As a premise of the following description, the respectiveconstitution elements (such as the pixel unit and the AD converter) ofthe NMOS solid state imaging device 100 are formed on one and the samechip (namely, on one semiconductor substrate).

[0055] First, the comparator 104 will be described. As shown in FIG. 1,the comparator 104 generates the synthesized signal from the analogpixel signal output from each column of the pixel unit 101 and the rampsignal output from the ramp waveform generator 109, compares thesynthesized signal with the reference voltage generated within thecomparator 104 and rapidly transfers the comparison result to the memory105. Transistors included in the comparator 104 are N-type MOStransistors alone, and in this embodiment, in order to prevent problemsof signal voltage level attenuation, power consumption increase,response speed lowering and the like peculiar to a circuit composed ofN-type MOS transistors, the comparator 104 is provided with circuitalspecific means as follows: The comparator 104 uses three invertercircuits connected in series to one another. In this case, among thethree inverter circuits, one disposed at the input initial stage(namely, the first stage) is designed, in order to increase its fallspeed, so that the ON resistance of a transistor connected to GNDpotential can be relatively small and the ON resistance of a transistorconnected to power potential can be relatively large. Also, the invertercircuit disposed at the second stage is designed, in order to increaseits rise speed, so that the ON resistance of a transistor connected topower potential can be relatively small and the ON resistance of atransistor connected to GND potential can be relatively large. Inaddition, the inverter circuit disposed at the third stage is designed,in order to increase its fall speed, so that the ON resistance of atransistor connected to GND potential can be relatively small and the ONresistance of a transistor connected to power potential can berelatively large. Furthermore, in order to prevent the voltageattenuation of its output pulse and to accelerate the output pulse, thecomparator 104 includes a booster circuit. Since the circuit is thusdesigned with emphasis placed on the increase of the fall speed from“High” level to “Low” level of the ultimate output characteristic of theinverter circuit disposed at the third stage, even though N-MOStransistors alone are used in the circuit, the signal voltage level canbe kept, the consumption power can be reduced and the response speed canbe increased so as to attain performances at practical levels.

[0056]FIG. 2 is a block diagram for showing an example of the circuitconfiguration (of a portion corresponding to six pixel columns) of thecomparator 104 of this embodiment, FIG. 3 is a block diagram for showingthe detailed circuit configuration of a portion corresponding to onepixel column of the comparator 104 of FIG. 2, and FIG. 4 is an operationtiming chart of the comparator 104 of FIG. 2. In FIGS. 2 and 3, M19through M29 indicate N-type MOS transistors, C20 through C23 indicatecapacitors and I21 through I23 indicate inverter circuits.

[0057] As shown in FIGS. 2 through 4, in the comparator 104, first, whena pixel signal input switch SIGSW is set to “High” level with an analogpixel signal SIG held at a reset level in a horizontal blanking period,the transistor M20 is turned on so as to input the pixel signal SIG atthe reset level. Next, when a comparator reset switch CMPRS is set to“High” level, the transistor M22 is turned on so as to remove thresholdvariation of the transistor M23 and threshold variation of the amplifiertransistors of the respective pixels, and then, the pixel signal SIG isread from the photodiode of each pixel. Thereafter, when a ramp signalinput switch SAWSW is set to “High” level, the transistor M19 is turnedon so as to input a ramp signal, and thus, a synthesized signal of theramp signal and the pixel signal SIG is allowed to appear on a node VIN(see FIG. 3). At this point, the ramp waveform is adjusted so that theinitial value of the voltage on the node VIN can be always lower thanthe threshold variation of the transistor M23. Subsequently, as the rampsignal is linearly swept, the voltage on the node VIN also increases,and when the voltage on the node VIN becomes higher than the thresholdvoltage of the transistor M23, potential on a node N22 becomes “Low”level, potential on a node N24 becomes “High” level and a comparatoroutput signal CMPOUT undergoes a “Low” transition.

[0058] Significant points to be realized by the comparator 104 are that“High” level corresponding to the initial value of the comparator outputsignal CMPOUT is power voltage (power potential) level, and that thefall speed of the comparator output signal CMPOUT from “High” level to“Low” level is as fast as possible. This is because, in the memory 105(see FIG. 5) disposed at the subsequent stage of the comparator 104, anN-type MOS transistor M30 is controlled in accordance with thecomparator output signal CMPOUT so as to store a counter value.

[0059] Therefore, in this embodiment, the dimensions of the three stagesof inverter circuits I21 through I23 all using N-MOS transistors aloneis devised. Specifically, the inverter circuits are designed withemphasis placed on the fall characteristic in the inverter circuit I21disposed at the first stage, with emphasis placed on the risecharacteristic in the inverter circuit I22 disposed at the second stage,and with emphasis placed on the fall characteristic in the invertercircuit I23 disposed at the third stage.

[0060] More specifically, in the inverter circuit I21 disposed at thefirst stage, the ON resistance of the transistor M23 is reduced bymaking the gate length relatively small and the gate width relativelylarge in the transistor M23 used for driving to “Low” level, and thus,the fall speed of the inverter circuit I21 disposed at the first stagecan be increased. On the other hand, the ON resistance of the transistorM21 is increased by making the gate length relatively large and the gatewidth relatively small in the transistor M21 used for driving to “High”level, and thus, the current is reduced. Since the transistor M21 of theinverter circuit I21 is a depletion type transistor, the “High”potential in the inverter circuit I21 disposed at the first stage andprovided with the booster circuit is the same as the power potential(i.e., the power voltage VDD). FIG. 18 is a cross-sectional view of thetransistor M21 included in the inverter circuit I21 disposed at thefirst stage. As shown in FIG. 18, in a semiconductor substrate 200 ofthe same conductivity type as that of the transistor M21, namely, asemiconductor substrate 200 on which the NMOS solid state imaging device100 of this embodiment is built, wells 201 and 202 of a conductivitytype different from that of the semiconductor substrate 200 are formed.In this case, the well 202 is independent of the well 201. Also, anN-type MOS transistor other than the transistor M21 is formed above thewell 201, and the transistor M21 alone is formed above the well 202.Specifically, a gate electrode 206 is formed above the well 202 with aninsulating film 203 sandwiched therebetween. Also, on both sides of thegate electrode 206 in the well 202, a drain region 204 and a sourceregion 205 are formed. Furthermore, the source region 205 and the gateelectrode 206 of the transistor M21 are set to have the same potentialas the well 202 through an interconnect 207. Although not shown in thedrawing, the source region 205 and the gate electrode 206 are connectedto the drain of the transistor M23 through the interconnect 207.Furthermore, the drain region 204 of the transistor M21 is connected tothe power source through an interconnect 208.

[0061] Also, in the inverter circuit 122 disposed at the second stage,the ON resistance of the transistor M25 is reduced by making the gatelength relatively small and the gate width relatively large in thetransistor M25 used for driving to “High” level. Furthermore, when theinverter I21 disposed at the first stage outputs a signal at “High”level, the transistor M24 is turned on so that a voltage obtained bysubtracting the threshold voltage of the transistor M24 from the powerpotential VDD can be applied to the gate of the transistor M25.Moreover, when the inverter circuit I21 outputs a signal at “Low” level,a voltage boosted to exceed the power voltage VDD is applied to the gateof the transistor M25, and hence the transistor M25 becomes completelyconductive. In other words, the inverter circuit I22 is provided withthe booster circuit having the transistor M25 whose source or drain isconnected to the power potential VDD. As a result, the rise speed of theinverter circuit I22 disposed at the second stage can be increasedwithout causing the voltage attenuation. On the other hand, the ONresistance of the transistor M26 is increased by making the gate lengthrelatively large and the gate width relatively small in the transistorM26 used for driving to “Low” level, and thus, the current is reduced.

[0062] Moreover, in the inverter circuit 123 disposed at the thirdstage, the ON resistance of the transistor M29 is reduced by making thegate length relatively small and the gate width relatively large in thetransistor M29 used for driving to “Low” level, and thus, the fall speedof the inverter circuit 123 disposed at the third stage is increased. Onthe other hand, the ON resistance of the transistor M28 is increased bymaking the gate length relatively large and the gate width relativelysmall in the transistor M28 used for driving to “High” level, and thus,the current is reduced. It is noted that a voltage obtained bysubtracting the threshold voltage of the transistor M27 from the powerpotential VDD is applied to the gate of the transistor M28 in order tooutput a signal at “High” level without attenuating it to be smallerthan the power potential VDD. Also, when the inverter circuit 122disposed at the second stage outputs a signal at “Low” level, a voltageboosted to exceed the power potential VDD is applied to the gate of thetransistor M28, and hence, the transistor M28 becomes completelyconductive. In other words, the inverter circuit I23 is provided withthe booster circuit having the transistor M28 whose source or drain isconnected to the power potential VDD. In this manner, a signal at “High”level can be output without causing the voltage attenuation.

[0063] Through the circuit design described above, the fall speed of thecomparator output signal CMPOUT of the comparator 104 can be improvedand the power consumption of the comparator 104 can be reduced.

[0064] Next, the memory 105 will be described. As shown in FIG. 1, thememory 105 interrupts the counter value input from the counter generator107 in accordance with a “Low” signal output as a result of thecomparison operation of the comparator 104, and stores the counter valueinput at the interruption in a counter value storage capacitor. Also,the memory 105 reads the stored counter value in time series inaccordance with the pulse (the column selection signal) supplied fromthe horizontal scanner 103 and successively outputs the read countervalue through an output amplifier to the outside (the signal processor150) as a digital signal. At this point, since transistors included inthe memory 105 are all N-type MOS transistors as in the comparator 104,the memory 105 includes a booster circuit in order to prevent theproblems of the signal voltage level attenuation, the consumption powerincrease and the response speed lowering, so as to attain performancesat the practical levels. Furthermore, in order to reduce the circuitscale, circuit elements included in the memory 105 are shared as much aspossible on the basis of the characteristics of their operations.

[0065]FIG. 5 is a block diagram for showing an example of the circuitconfiguration (of a portion corresponding to six pixel columns) of thememory 105 of this embodiment, FIG. 6 is a block diagram for showing thedetailed circuit configuration of a portion corresponding to one pixelcolumn of the memory 105 of FIG. 5, and FIG. 7 is an operation timingchart of the memory 105 of FIG. 5. In FIGS. 5 and 6, M30 through M34 andM40 through M48 indicate N-type MOS transistors, C30 and C40 through C43indicate capacitors, Lat indicates a latch circuit and AMP indicates anamplifier.

[0066] As shown in FIGS. 5 through 7, in the latch circuit Lat of thememory 105, first, when the comparator output signal COMPOUT from thecomparator 104 undergoes a “Low” transition in a horizontal blankingperiod, the transistor M30 is turned off, so that a counter code (adigital value) supplied from the counter generator 107 can be sampled tobe pre-fetched by the pre-fetching capacitor C30. Next, when a latchdata transfer signal DATATR undergoes a “High” transition, thetransistor M31 is turned on, so that the pre-fetched counter code can beapplied to the gate of the transistor M34. In this manner, data reversedto the counter code data (namely, inverted data) appears on the drain(on the side of the transistor M33) of the transistor M34. A pulse (acolumn selection signal HSR) supplied from the horizontal scanner 103 issuccessively applied to the gate of the transistor M33, and as a result,the inverted data of the pre-fetched counter code is input as a timeseries signal to the amplifier AMP that outputs inverted data. After theinverted data of the counter code is input to the amplifier AMP, a dataclear signal DATACLR undergoes a “High” transition so as to clear chargeof each pre-fetching capacitor C30, and the transistor M32 is turned on.

[0067] Next, in the amplifier AMP provided in the memory 105 forexternally outputting a digital value resulting from AD conversion, anoperation start pulse (an inverter start 1 signal) INVSTA1 for operatingan inverter circuit disposed at the first stage is turned on, andsubsequently, an operation start pulse (an inverter start 2 signal)INVSTA2 for operating an inverter circuit disposed at the second stageis turned on. Thus, the amplifier AMP can be previously placed in anoperation state. At this point, as described above, the transistor M33is turned on through the “High” transition of the column selectionsignal HSR supplied from the horizontal scanner 103 and the pre-fetchedcounter code is input to the amplifier AMP through the transistor M33 asa digital signal. In this manner, the digital signal obtained byconverting the analog pixel signal is ultimately amplified by theamplifier AMP to be output to the outside. In the amplifier AMP, theconsumption power can be reduced by using an inverter operation stoppulse (an inverter stop signal) INVSTP when the amplifying operation isnot necessary. Furthermore, since the inverter circuit included in theamplifier AMP has a booster circuit, “High” level can be set to thepower potential, and hence, the voltage attenuation of the output signalcan be prevented and the output signal can be accelerated. The specificoperation of the booster circuit is as follows: When the inverter start1 signal INVSTA1 is turned on, voltages respectively obtained bysubtracting the threshold voltages of the transistors M40 and M43 fromthe power potential VDD are respectively applied to the gates of thetransistors M41 and M44 included in the booster circuit of each invertercircuit. When potential at the gate of the transistor M34 becomes “Low”,a voltage boosted to exceed the power potential VDD is applied to thegate of the transistor M41, and therefore, the transistor M41 becomescompletely conductive. Accordingly, a signal at “High” level can beoutput without causing the voltage attenuation. Similarly, whenpotential at the gate of the transistor M34 becomes “High”, a voltageboosted to exceed the power potential VDD is applied to the gate of thetransistor M44, and therefore, the transistor M44 becomes completelyconductive. Therefore, a signal at “High” level can be output withoutcausing the voltage attenuation. The source or the drain of each of thetransistors M41 and M44 is connected to the power potential VDD.

[0068] When the above-described booster circuit is used, the rise speedfor outputting a signal at “High” level can be easily increased, but thefall speed for outputting a signal at “Low” level is difficult toincrease. Therefore, in this embodiment, the gate lengths of thetransistor M34 for driving the output of the latch circuit Lat to “Low”level and the transistor M46 for driving the output of the amplifier AMPto “Low” level are made relatively small, and the gate widths of thesetransistors M34 and M46 are made relatively large. Thus, the ONresistances of these transistors are reduced, so that the fall speed canbe increased.

[0069] Next, the pulse generator 106 will be described. As shown in FIG.1, the pulse generator 106 generates a timing pulse necessary for the ADconversion through synthesis of the output pulse (the column selectionsignal) supplied from the horizontal scanner 103, and inputs thegenerated pulse to the counter generator 107 disposed at the subsequentstage.

[0070]FIG. 8 is a block diagram for showing an example of the circuitconfiguration of the pulse generator 106 of this embodiment, and FIG. 9is an operation timing chart of the pulse generator 106 of FIG. 8. InFIGS. 8 and 9, M1 through M4 indicate N-type MOS transistors and C1indicates a capacitor.

[0071] As shown in FIGS. 8 and 9, the pulse generator 106 of thisembodiment generates a new pulse by using fall edges of two kinds ofpulses output in time series from the horizontal scanner 103. Also, thepulse generator 106 includes a plurality of inverter circuits (that is,inverter circuits of two stages in this embodiment) connected in seriesto one another, and a booster circuit is provided to the invertercircuit at the ultimate stage out of the plural inverter circuits.Specifically, in the pulse generator 106, when an input signal INPUT1supplied from the horizontal scanner 103 undergoes a “High” transition,the transistor M1 is turned on, and therefore, a voltage [the powerpotential VDD—the threshold voltage of the transistor M1] is applied tothe bootstrap capacitor C1 to charge the capacitor C1 and this voltageis also applied to the gate of the transistor M3. Therefore, a voltage[the power potential VDD—the threshold voltage of the transistor M3]appears as an output signal OUTPUT of the pulse generator 106. Thus, avoltage on a node N1 is boosted, and the boosted voltage is applied tothe gate of the transistor M3. In other words, a voltage not less thanthe power potential VDD is applied to the gate of the transistor M3 thatis included in the booster circuit and is connected to the powerpotential VDD at its source or drain. Therefore, a “High” signal at thelevel of the power potential VDD appears as the output signal OUTPUT. Onthe other hand, when an input signal INPUT2 supplied from the horizontalscanner 103 undergoes a “High” transition, the transistors M2 and M4 areturned on. Therefore, the potential on the node N1 and the output signalOUTPUT are driven to GND level, so that a “Low” signal appears as theoutput signal OUTPUT. Through this operation principle, the pulsegenerates 106 generates, from the pulse supplied from the horizontalscanner 103, pulses necessary for the AD conversion and the counter codegeneration.

[0072] Next, the counter generator 107 will be described. As shown inFIG. 1, the counter generator 107 accepts, as inputs, the output pulsefrom the horizontal scanner 103 and the pulse generated by the pulsegenerator 106, generates data (a counter value) working as a digitaloutput value resulting from the AD conversion and outputs the generateddata to the memory 105.

[0073]FIG. 10 is a block diagram for showing an example of the circuitconfiguration of the counter generator 107 using frequency dividercircuits of this embodiment, FIG. 11 is a block diagram for showing theconfiguration of one frequency divider circuit of the counter generator107 of FIG. 10, and FIG. 12 is an operation timing chart of the countergenerator 107 of FIG. 10. In FIG. 11, M51 through M74 indicate N-typeMOS transistors and C51 through C54 indicate capacitors.

[0074] As shown in FIGS. 10 through 12, the operation of the countergenerator 107 is first started by using the pulse generated by the pulsegenerator 106 and a reference pulse input from the signal processor 150to the horizontal scanner 103. Then, when a pulse to be divided is inputwhile a division start pulse input CODEnSTA (n=0 through 9) is at “High”level, a signal whose polarity is inverted in synchronization with thepulse to be divided appears as a divide-by-2 subharmonic pulse outputCODEn (n=0 through 9). Next, when the pulse to be divided is input withthe division start pulse input CODEnSTA placed at “Low” level, thesignal whose polarity is inverted in synchronization with the pulse tobe divided appears again as the divide-by-2 subharmonic pulse outputCODEn. In the counter generator 107, the frequency divider circuits eachhaving the configuration shown in FIG. 11 are cascaded so as to generatethe counter value necessary for the AD conversion through theabove-described operation principle.

[0075] The frequency divider circuit shown in FIG. 11 contains aplurality of inverter circuits each including a booster circuit. Theoperation of this booster circuit is as follows: Voltages respectivelyobtained by subtracting the threshold voltages of the transistors M52,M56 and M59 from the power potential VDD are previously appliedrespectively to the gates of the transistors M53, M57 and M60 that areincluded in the booster circuit and are connected to the power potentialVDD at their sources or drains. Then, when potentials at the gates ofthe transistors M54, M58 and M61 respectively disposed on the drivesides of the transistors M53, M57 and M60 are at “Low” level, voltagesboosted to exceed the power potential VDD are applied to the gates ofthe transistors M53, M57 and M60, and therefore, the transistors M53,M57 and M60 become completely conductive. Thus, a signal at “High” levelcan be output without causing the voltage attenuation.

[0076] When the above-described booster circuit is used, the rise speedfor outputting a signal at “High” level can be easily increased, but thefall speed for outputting a signal at “Low” level is difficult toincrease. Therefore, in this embodiment, the gate lengths of thetransistors M54, M58 and M61 for driving the outputs of the respectiveinverter circuits of the frequency divider circuit of FIG. 11 to “Low”level are made relatively small, and the gate widths of thesetransistors M54, M58 and M61 are made relatively large. Thus, the ONresistances of these transistors are reduced, so that the fall speed canbe increased.

[0077] Next, the DA converter 108 and the ramp waveform generator 109will be described. As shown in FIG. 1, the DA converter 108 accepts, asan input, the code data (the counter value) generated by the countergenerator 107 and generates an analog signal. Also, the ramp waveformgenerator 109 accepts, as inputs, an analog signal generated by the DAconverter 108 and the pulse generated by the pulse generator 106, andgenerates a ramp signal necessary for the comparator 104. In this case,transistors included in the DA converter 108 and the ramp waveformgenerator 109 are all N-type MOS transistors.

[0078]FIG. 13 is a block diagram for showing an example of the circuitconfiguration of the DA converter 108 of this embodiment, FIG. 14 is ablock diagram for showing an example of the circuit configuration of theramp waveform generator 109 of this embodiment, and FIG. 15 is anoperation timing chart of the ramp waveform generator 109 of FIG. 14. InFIG. 13, M80 through M89 indicate N-type MOS transistors, I80 throughI89 indicate inverter circuits, and R and 2R are resistors. Also, inFIG. 14, M90 through M93 indicate N-type MOS transistors, C90 and C91indicate capacitors, and V90 and V91 indicate power sources.

[0079] First, as shown in FIG. 13, each bit of the counter value (thecode data CODEn) generated by the counter generator 107 is input to theDA converter 108. Also, the DA converter 108 is an R-2R type DAconverter, and hence outputs potential in proportion to the countervalue as an analog out signal ANAOUT. The analog out signal ANAOUT has alinearly sweeping waveform such as a saw tooth wave (see FIG. 15).Subsequently, in the ramp waveform generator 109 shown in FIG. 14, apulse (a reset pulse) generated by the pulse generator 106 and theanalog out signal ANAOUT generated by the DA converter 108 are appliedat timing shown in FIG. 15, so as to generate a ramp signal having awaveform necessary for the AD conversion. Specifically, first, charge ofthe capacitor C90 is cleared by using the reset switch (transistor) M91,and at the same time, the DC cramp switch (transistor) M92 is turned onso as to once keep the signal level of the ramp signal at potential ofthe power source V90. Next, the offset level setting switch (transistor)M93 is turned on so as to keep the output level of the ramp signal atpotential of the power source V91. Then, after the reset switch(transistor) M91 is turned off, the analog out switch (transistor) M90is turned on. Thus, a linearly sweeping waveform similar to the analogout signal ANAOUT appears on the basis of the offset level as the rampsignal output.

[0080] As described so far, according to the NMOS solid state imagingdevice of this embodiment, the design of the respective constitutionelements (such as the comparator 104 and the memory 105) is optimized byusing N-type MOS transistors alone as transistors included therein, soas to convert an analog signal output from the amplifier included ineach pixel 101 a belonging to a pixel row selected in the pixel unit 101into a digital signal. In other words, the AD converter using N-type MOStransistors alone as transistors included therein can be contained inthe NMOS solid state imaging device. Therefore, an NMOS solid stateimaging device capable of digital output can be realized, resulting inremarkably improving the additional value of the NMOS solid stateimaging device.

[0081] Furthermore, according to the NMOS solid state imaging device ofthis embodiment, the booster circuit is provided in the comparator 104,and the fall speed from “High” level to “Low” level of the ultimateoutput characteristic of the inverter circuit I23 disposed at the thirdstage of the comparator 104 is increased. Accordingly, even thoughN-type MOS transistors alone are used, the problems of the signalvoltage level attenuation, the consumption power increase and theresponse speed lowering can be prevented.

[0082] Moreover, according to the NMOS solid state imaging device ofthis embodiment, the circuit elements are shared in accordance withtheir operation characteristics in the memory 105, and therefore, thecircuit scale can be reduced. Also, since the booster circuit isprovided in the amplifier AMP included in the memory 105, even thoughN-type MOS transistors alone are used, the problems of the signalvoltage level attenuation, the consumption power increase and theresponse speed lowering can be prevented. As a result, the NMOS solidstate imaging device can attain performances at the practical levels.

[0083] In addition, since the NMOS solid state imaging device of thisembodiment includes the pulse generator 106 for generating a pulsesignal on the basis of a column selection signal output by thehorizontal scanner 103, a pulse generation circuit included in a signalprocessor such as a DSP externally provided to a conventional solidstate imaging device can be omitted.

[0084] Furthermore, according to the NMOS solid state imaging device ofthis embodiment, since the counter generator 107 for generating acounter value includes the booster circuit for preventing the voltageattenuation of the output signal and accelerating the output signal, theproblems of the signal voltage level attenuation, the consumption powerincrease and the response speed lowering can be more definitelyprevented.

[0085] Although the comparator 104 and the memory 105 are separatelyprovided in this embodiment, a comparison/storage unit having both thefunctions of the comparator and the memory can be provided instead.

[0086] Although the amplifier AMP is provided as a part of the memory105 in this embodiment, the amplifier AMP may be provided separatelyfrom the memory 105 instead.

What is claimed is:
 1. A solid state imaging device using N-type MOStransistors alone as transistors included therein, comprising: a pixelunit composed of a plurality of pixels arranged in a two-dimensionalmatrix, each of said pixels including a photoelectric converting elementfor generating charge in response to light and an amplifying element foroutputting, as an analog signal, a voltage signal corresponding to saidcharge generated by said photoelectric converting element; a selectionsignal line provided correspondingly to each pixel row of said pixelunit; a comparison/storage unit provided correspondingly to each pixelcolumn of said pixel unit for converting, into a digital signal, saidanalog signal output from said amplifying element included in each pixelbelonging to a pixel row selected in said pixel unit and for storingsaid digital signal; a scanner for selecting and reading said digitalsignal stored in said comparison/storage unit in time series; and anamplifier for amplifying said read digital signal and outputting saidamplified digital signal to the outside.
 2. The solid state imagingdevice of claim 1, wherein said comparison/storage unit includes acomparator, which includes three inverter circuits using N-type MOStransistors alone and serially connected to one another, and a boostercircuit for preventing voltage attenuation of an output signal andaccelerating said output signal, in order to increase a fall speed of aninverter circuit disposed at the first stage out of said three invertercircuits, ON resistance of a transistor connected to GND potential isset to be smaller than ON resistance of a transistor connected to powerpotential in said inverter circuit disposed at the first stage, in orderto increase a rise speed of an inverter circuit disposed at the secondstage out of said three inverter circuits, ON resistance of a transistorconnected to the power potential is set to be smaller than ON resistanceof a transistor connected to the GND potential in said inverter circuitdisposed at the second stage, and in order to increase a fall speed ofan inverter circuit disposed at the third stage out of said threeinverter circuits, ON resistance of a transistor connected to the GNDpotential is set to be smaller than ON resistance of a transistorconnected to the power potential in said inverter circuit disposed atthe third stage.
 3. The solid state imaging device of claim 2, whereinsaid comparison/storage unit includes a memory, which includes a firstswitch for reading a counter value on the basis of a signal suppliedfrom said comparator, a capacitor for storing said read counter value, asecond switch for transferring said counter value stored in saidcapacitor, a third switch for deleting said transferred counter value, afourth switch for reading said transferred counter value on the basis ofa signal supplied from said scanner, and said amplifier for outputtingsaid read counter value to the outside, and said amplifier includes abooster circuit for preventing voltage attenuation of an output signalthereof and accelerating said output signal.
 4. The solid state imagingdevice of claim 3, further comprising: a pulse generator for generatinga pulse signal on the basis of a column selection signal output from ahorizontal scanner included in said scanner; and a counter generator forgenerating said counter value on the basis of said pulse signalgenerated by said pulse generator.
 5. The solid state imaging device ofclaim 4, wherein said counter generator includes a booster circuit forpreventing voltage attenuation of an output signal thereof andaccelerating said output signal.
 6. The solid state imaging device ofclaim 4, further comprising a ramp waveform generator for generating aramp signal on the basis of said pulse signal generated by said pulsegenerator and said counter value generated by said counter generator. 7.A solid state imaging device, comprising: a pixel unit formed on asemiconductor substrate and outputting, as an analog signal, a voltagesignal corresponding to light; and an AD converter formed on saidsemiconductor substrate and converting said analog signal output fromsaid pixel unit into a digital signal, wherein transistors included insaid pixel unit and said AD converter are all N-type MOS transistors,and said AD converter includes a booster circuit.
 8. The solid stateimaging device of claim 7, wherein said booster circuit includes atransistor whose source or drain is connected to power potential, and avoltage not less than said power potential is applied to a gate of saidtransistor.
 9. The solid state imaging device of claim 7, wherein saidAD converter includes, in addition to said booster circuit, any or allof a comparator, a memory, a pulse generator and a counter generator.10. The solid state imaging device of claim 9, wherein said comparatorincludes an inverter circuit having said booster circuit, said boostercircuit includes a first transistor whose source or drain is connectedto power potential, and a voltage not less than said power potential isapplied to a gate of said first transistor.
 11. The solid state imagingdevice of claim 9, wherein said comparator includes an inverter circuithaving said booster circuit, said inverter circuit has a secondtransistor formed above a well region independent of other well regions,and a gate and a source of said second transistor are electricallyconnected to said well region.
 12. The solid state imaging device ofclaim 9, wherein said memory includes a plurality of switches, acapacitor and an output amplifier, said output amplifier includes abooster circuit, said booster circuit has a transistor whose source ordrain is connected to power potential, and a voltage not less than saidpower potential is applied to a gate of said transistor.
 13. The solidstate imaging device of claim 12, further comprising a scanner forselecting and reading a digital signal obtained by said AD converter intime series, wherein said memory includes a first switch for reading acounter value on the basis of a signal supplied from said comparator, acapacitor for storing said read counter value, a second switch fortransferring said counter value stored in said capacitor, a third switchfor deleting said transferred counter value, a fourth switch for readingsaid transferred counter value on the basis of a signal supplied fromsaid scanner, and an output amplifier for outputting said read countervalue to the outside.
 14. The solid state imaging device of claim 9,further comprising a scanner for selecting and reading a digital signalobtained by said AD converter in time series, wherein said pulsegenerator generates a pulse signal on the basis of a column selectionsignal output from a horizontal scanner included in said scanner andincludes a plurality of inverter circuits serially connected to oneanother, an inverter circuit disposed at the ultimate stage out of saidplurality of inverter circuits includes a booster circuit, said boostercircuit has a transistor whose source or drain is connected to powerpotential, and a voltage not less than said power potential is appliedto a gate of said transistor.
 15. The solid state imaging device ofclaim 9, wherein said counter generator generates a counter value on thebasis of a pulse signal generated by said pulse generator and includes aplurality of inverter circuits each having a booster circuit, saidbooster circuit has a transistor whose source or drain is connected topower potential, and a voltage not less than said power potential isapplied to a gate of said transistor.